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L5989D
4 A continuous (more than 5 A pulsed) step-down switching regulator with synchronous rectification
Features

4 A output current (more than 5 pulsed) Operating input voltage from 2.9 V to 18 V External 1.8 V 2% reference voltage Output voltage from 0.6 to input voltage MLCC compatible 200 ns TON Programmable UVLO matches 3.3 V, 5 V and 12 V bus FSW programmable up to 1 MHz Voltage feed-forward Zero load current operation Programmable current limit on both switches Programmable sink current capability Pre-bias start up capability Thermal shutdown

HTSSOP 16
Applications
Consumer: STB, DVD, LCD TV, VCR, car radio, LCD monitors Networking: XDSL, modems, routers and switches Computer and peripherals: printers, audio / graphic cards, optical storage, hard disk drive Industrial: DC DC modules, factory automation
Figure 1.
Test application circuit
L5989D
June 2009
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Contents
L5989D
Contents
1 2 3 4 5 Description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 Pin function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 Functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12
5.1 5.2 5.3 5.4 5.5 Multifunction pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 Oscillator . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 External voltage reference . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 Monitoring and protections . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
5.5.1 5.5.2 5.5.3 5.5.4 Overvoltage . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 Current limiting . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 UVLO . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Thermal shutdown . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22
5.6 5.7 5.8
Power Good . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Minimum on time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 22 Error amplifier . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23
6
Application information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24
6.1 6.2 6.3 6.4 Input capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 24 Inductor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Output capacitor selection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27
6.4.1 6.4.2 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 28 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32
6.5 6.6 6.7 6.8
R.M.S. current of the embedded power MOSFETs . . . . . . . . . . . . . . . . . 35 Thermal considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Layout considerations . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 39 Application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41
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Contents
7 8 9 10
Typical characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Package mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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List of table
L5989D
List of table
Table 1. Table 2. Table 3. Table 4. Table 5. Table 6. Table 7. Table 8. Table 10. Table 11. Table 12. Table 13. Table 14. Table 15. Table 16. Table 17. Pinout description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Thermal data. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 8 Electrical characteristic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 A/D voltage windows . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 UOS voltage biasing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 FSW resistor examples. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 ILIM-ADJ resistor examples . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Input capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 25 Inductors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 26 Output capacitors . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 27 Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 42 Component list . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 43 HTSSOP16 mechanical data . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 47 Order codes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 49 Document revision history . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 50
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L5989D
List of figures
List of figures
Figure 1. Figure 2. Figure 3. Figure 4. Figure 5. Figure 6. Figure 7. Figure 8. Figure 9. Figure 10. Figure 11. Figure 12. Figure 13. Figure 14. Figure 15. Figure 16. Figure 17. Figure 18. Figure 19. Figure 20. Figure 21. Figure 22. Figure 23. Figure 24. Figure 25. Figure 26. Figure 27. Figure 28. Figure 29. Figure 30. Figure 31. Figure 32. Figure 33. Figure 34. Figure 35. Figure 36. Figure 37. Figure 38. Figure 39. Figure 40. Test application circuit . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 Pin connection . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 Voltage mode control loop . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Internal block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 12 Oscillator circuit block diagram . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 Sawtooth: voltage feed forward . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 Sawtooth: frequency adjust . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16 OVP not latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 OVP latched . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 Constant current protection at extreme duty cycles . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 Minimum TON. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 23 Type III compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 29 Open loop gain bode diagram with ceramic output capacitor . . . . . . . . . . . . . . . . . . . . . . . 31 Type II compensation network . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Open loop gain: module bode diagram. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 32 Open loop gain bode diagram with high ESR output capacitor . . . . . . . . . . . . . . . . . . . . . 34 Maximum continuos output current vs. duty cycle . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 35 Switching losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36 Estimation of the internal power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37 Estimation of the internal power losses . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38 Measurement of the thermal impedance of the evaluation board. . . . . . . . . . . . . . . . . . . . 39 Top board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 40 Bottom board layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 41 Demonstration board application circuit (fSW = 400 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 41 Demonstration board application circuit (fSW = 600 kHz) . . . . . . . . . . . . . . . . . . . . . . . . . 43 Junction temperature vs. fSW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Junction temperature vs. fSW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Junction temperature vs. fSW. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Junction temperature vs. VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44 Junction temperature vs. VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Junction temperature vs. VOUT . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Efficiency vs. output current . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Load regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 45 Line regulation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Load transient from 0 to 3 A . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Soft-start . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 46 Mechanical drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 48
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Description
L5989D
1
Description
The L5989D is a monolithic step down power switching regulator able to deliver a continuos output current of 4 A to the load in most of the application conditions limited only by the thermal performance (see Chapter 6.5 for details). The device is able to deliver more than 5 A to the load for a maximum time which is dependent on the thermal impedance of the system and the specific operating conditions (see Chapter 6.6). The input voltage can range from 2.9 V to 18 V. The device is capable of 100% duty cycle operation thanks to the embedded high side PMOS switch which doesn't need external bootstrap capacitor to be driven. The internal switching frequency is adjustable by external resistor and can be set continuously from 100 kHz to 1 MHz. The multifunction UOS pin allows to set-up properly the additional embedded features depending on the value of the voltage level.

U (UVLO): two UVLO thresholds can be selected to match the 3.3 V and 5 V or 12 V input buses O (OVP): latched or not latched OVP protection selectable. In latched mode the switching activity is interrupted until an UVLO or INH event happens S (SINK): the sink capability is always disabled during soft-start time to support prebiased output voltage. Afterwards the sink capability can be enabled or not depending on the voltage set on the multifunction pin.
During soft-start phase a constant current protection is active to deliver extra current necessary to load the output capacitor. The current limit protection is achieved by sensing the current flowing in both embedded switches to assure an effective protection even at extreme duty cycle operations. Finished the soft-start phase the current protection feature triggers the "HICCUP" mode forcing the soft-start capacitor to be discharged and recharged. The current thresholds of both switches can be adjusted in tracking by using an external resistor to dimension the current protection accordingly to the local application. The soft-start time is based on a constant current charge of an external capacitor. As a consequence the time can be set accordingly to the value of the output capacitor. The latest smart power technology BCD6 (Bipolar-CMOS-DMOS version 6) features a low resistance of the embedded switches (35 m typical for a NMOS, 50 m typical for a PMOS), achieving high efficiency levels. The HTSSOP16 package with exposed pad accomplishes low RthJA (40C/W), useful in dissipating power internally generated during high output current / high frequency operations.
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L5989D
Pin function
2
Pin function
Figure 2. Pin connection
Table 1.
N. 1, 16 2, 3 4 5 6
Pinout description
Name OUT VIN VCC SS/INH COMP Regulator output Unregulated DC input voltage Unregulated DC signal input voltage An external logic signal (active LOW) disables the device. In case the pin is floating the device deliver a constant current (22 A typ.) to charge the soft-start capacitor (see Chapter 5.4) Error amplifier output for frequency compensation Connecting a pull-up resistor to VREF or a pull-down resistor to GND the internal current limit thresholds can be tuned to match the local application. In case the pin is left floating no changes are applied to the default current limit thresholds Feedback input. Connecting the output voltage directly to this pin results in a regulation voltage of 600 mV. An external resistive divider is required for higher output voltages Open collector output; low impedance if the feedback voltage is lower than 0.85 times the internal reference of the error amplifier. An hysteresis is provided Connecting a pull-up resistor to VREF or a pull-down resistor to GND the internal oscillator frequency will be increased or decreased respectively. In case the pin is left floating the predefined oscillator frequency (400 kHz 10%) is active Multifunction pin used to program additional features: UVLO thresholds, OVP latched/not latched, SINK enabled/disabled 1.8 V voltage reference Signal ground Power ground Description
7
ILIM-ADJ
8
FB
9
PGOOD
10
FSW
11 12 13 14, 15
U/O/S VREF SGND PGND
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Maximum ratings
L5989D
3
Maximum ratings
Table 2.
Symbol VCC VOUT Input voltage Output DC voltage
Absolute maximum ratings
Parameter Value 20 -0.3 (1) to VCC -0.3 to 4 1.5 2.25 -40 to 150 -55 to 150 Unit V V V V W C C
U/O/S, SS/INH, COMP, PGOOD, Analog pins Fsw, ILIM-ADJ FB Ptot TJ TSTG Feedback voltage Power dissipation at TA < 60 C Junction temperature range Storage temperature range
1. During the switching activity the negative peak voltage could reach -1.5 V without any damage for the device
Table 3.
Symbol RthJA
Thermal data
Parameter Thermal resistance junction to ambient max Value 40 (1) Unit C/W
1. HTSSOP16 package mounted on ST demonstration board
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L5989D
Electrical characteristics
4
Electrical characteristics
VCC = 12 V, TJ = 25 C unless otherwise specified. Table 4.
Symbol Vcc
Electrical characteristic
Parameter Operating input voltage range High side MOSFET on resistance Low side MOSFET on resistance Maximum peak limiting current Maximum valley limiting current Switching frequency Adjusted switching frequency Duty cycle Test condition Vout = 0.6 V; Iout = 3 A Min 2.9 76 Vcc = 4.0 V; Iout = 1.0 A
(1)
Typ
Max 18
Unit V m m m m A A kHz kHz
83 120 65 100 4 4.6 400 1000
90 132 70 106 4.4 5.06 440
Rdson HS
111 61
Rdson LS
Vcc = 4.0 V; Iout = 1.0 A
(1)
92 3.6 4.14 360
IL HIGH SIDE IL LOW SIDE fSW fSW ADJ D
ILIM-ADJ = float ILIM-ADJ = float FSW = floating RFSW PULL DWN = 27 k
0
100
%
Selectable undervoltage lock-out (UVLO) Turn ON Vcc threshold 3.3 V BUS Turn OFF Vcc threshold Turn ON Vcc threshold 12 V BUS Turn OFF Vcc threshold DC characteristic ISS Soft-start current Device ON level INH Device OFF level Iq Iq st-by Quiescent current Total stand-by quiescent current Duty Cycle = 0; VFB = 1 V 0.3 3 35 V mA A VSS/INH = 2 V VSS/INH = 0 0.8 22 5 A A V 6.8 7 V 2.5 2.6 8 8.5 V V 2.7 2.8 V
Dynamic characteristic (see figure 1) 0.595 VFB Voltage feedback 2.9 V < VCC < 18 V
(1)
0.6 0.6
0.605 V 0.609
0.592
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Electrical characteristics Table 4.
Symbol Error amplifier VOH VOL IO SOURCE High level output voltage Low level output voltage Source output current VFB = 0.2 V; SS floating VFB = 1.0 V VFB = 0.2 V VFB = 0.2 V VFB = 1.0 V
(2)
L5989D
Electrical characteristic (continued)
Parameter Test condition Min Typ Max Unit
3.1 0.1 25 5 40 100
V V mA mA mA dB
IO SRCE LIM Source current limitation IO SINK AV0 PGOOD Up threshold (VFB / VEAREF) Low threshold (VFB / VEAREF) VPGOOD Reference section Sink output current DC open loop gain
VFB rising VFB falling -5mA
81 76
85 80 0.4
89 84
% % V
1.756 VREF Reference voltage Vcc = 2.9 V to 18 V Vcc = 2.9 V to 18 V IREF = 0 mA IREF = 0 to 5 mA 12
(1)
1.8 1.8 6 7.5 18
1.837 1.852 12 15 24
V V mV mV mA
1.754
Line regulation Load regulation Short circuit current Protections Overvoltage trip (VFB / 0.6 internal ref.) Bus thresholds - UVLO 3.3 V bus - OVP not latched - No sink - UVLO 3.3 V bus - OVP not latched - Sink - UVLO 3.3 V bus - OVP latched - No sink - UVLO 3.3 V bus - OVP latched - Sink
VFB rising
17.5
20
22.5
%
TH1
(3)
0
0.2
V
TH2
(3)
0.26
0.425
V
TH3
(3)
0.48
0.65
V
TH4
(3)
0.71
0.875
V
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L5989D
Electrical characteristics Table 4.
Symbol
Electrical characteristic (continued)
Parameter - UVLO 12 V bus - OVP not latched - No sink - UVLO 12 V bus - OVP not latched - Sink - UVLO 12 V bus - OVP latched - No sink - UVLO 12 V bus - OVP latched - Sink Test condition
(3)
Min
Typ
Max
Unit
TH5
0.93
1.085
V
TH6
(3)
1.16
1.31
V
TH7
(3)
1.385
1.525
V
TH8
(3)
1.615
VREF
V
1. Specification over the junction temperature range (TJ) of -40 to +125 C are guaranteed by design, characterization and statistical correlation 2. Guaranteed by design 3. VCC = 4 V
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Functional description
L5989D
5
Functional description
The L5989D is based on a voltage mode control loop. Therefore the duty ratio of the internal switch is obtained through a comparison between a saw-tooth waveform (generated by an oscillator) and the output voltage of the error amplifier as shown in Figure 3. The advantage of this technique is the very short conduction time of the power elements thanks to the proper operation of the control loop without a precise current sense, which instead is required in current mode regulators. Thanks to this architecture the L5989D supports extremely low conversion ratio (D = VOUT/VIN) even at very high switching frequency (up to 1 MHz). Figure 3. Voltage mode control loop
The main internal blocks are represented in Figure 4. Figure 4. Internal block diagram
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L5989D
Functional description Below follows a brief description of the main blocks:

A voltage pre-regulator supplies the internal circuitry. The external 1.8 V voltage reference is supplied by this regulator. A voltage monitor circuit that checks the input and internal voltages A fully integrated sawtooth oscillator whose frequency is 400 kHz 10% when the Fsw pin is floating. Its frequency can be increased/decreased connecting a proper resistor to GND or VREF The internal current limitation circuitry monitors the current flowing in both embedded switches to guarantee an effective protection even in extreme duty cycle conditions The over voltage protection (OVP) monitors the feedback voltage. If the voltage of this pin overcomes the 20% of the internal reference value (600 mV 1%) it will force the conduction of the low side switch until the overshoot is present A voltage mode amplifier. The inverting input and the output are externally available for compensation A pulse width modulator (PWM) comparator and the relative logic to drive the embedded switches The soft-start circuit charges an external capacitor with a constant current equal to 20 A (typ.). The soft-start feature is realized clamping the output of the error amplifier until the voltage across the capacitor is below 2.7 V The PGOOD is an open collector output: low impedance if the feedback voltage is lower than 0.85 times the internal reference of the error amplifier. An hysteresis is provided The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. It recognizes eight different voltage windows of a VREF voltage magnitude for selecting additional features. An inhibit block for stand-by operation A circuit to realize the thermal protection function

5.1
Multifunction pin
The UOS pin is used to configure the device additional features accordingly to the voltage bias imposed through VREF voltage partitioning. The selectable options are:

UVLO level: two pre-defined the under voltage lock out thresholds can be selected to match the 3.3 V and 5 V or 12 V power bus SINK capability: this feature is always disabled during the soft-start period to be compatible with pre-biased output voltages. After the soft-start phase, the synchronous rectification can be enabled or not depending on the status of the UOS pin. Anyway, in case an overvoltage is detected, the sink capability is always enabled to bring the FB back to regulation as fast as possible OVP management: in case the latched mode is selected and an overvoltage event recurs, the switching activity will be suspended until VCC is reapplied or the SS/INH pin is toggled. Otherwise when the overvoltage transient is ended the regulator will work accordingly to the load request without regulation discontinuity
The circuitry related to the UOS multifunction pin is composed of a 3 bit A/D converter and the decoding logic. Table 5 shows the internal thresholds of each voltage window
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Functional description
L5989D
composing the VREF magnitude. The voltage biasing of the multifunction can be set accordingly to table Table 6. Table 5. A/D voltage windows
UVLO 1.8 V 1.575 V 1.35 V 1.125 V 0.9 V 0.675 V 0.45 V 0.225 V 0V OVP SINK
12 V BUS 12 V BUS 12 V BUS 12 V BUS 3.3 V BUS 3.3 V BUS 3.3 V BUS 3.3 V BUS
Latch Latch No latch No latch Latch Latch No latch No latch
Sink No sink Sink No sink Sink No sink Sink No sink
Table 6.
R1 (k) 0 0.68 1.2 2 3.3 6.2 11 N.C.
UOS voltage biasing
R2 (k) N.C. 2.7 2.7 2.7 2.7 2.7 2.7 0 VOUS(V) 1.8 1.438 1.246 1.034 0.810 0.546 0.355 0 UVLO 12 V bus 12 V bus 12 V bus 12 V bus 3.3 V bus 3.3 V bus 3.3 V bus 3.3 V bus OVP Latch Latch No latch No latch Latch Latch No latch No latch SINK Sink No sink Sink No sink Sink No sink Sink No sink
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Functional description
5.2
Oscillator
The generation of the internal saw-tooth waveform is based on the constant current charge / discharge of an internal capacitor. The current generator is designed to get a switching frequency of 400 kHz 10% in case the FSW pin is left floating. The current mirror connected to FSW (see Figure 5) pin acts increasing / decreasing the value of the internal charging current to adjust the oscillator frequency. Since the internal circuitry forces the FSW voltage bias at 1.235 V, the user can easily source / sink current in this pin connecting a pull up resistor to VREF or a pull down to GND respectively. Figure 5.
VREF Clock
Oscillator circuit block diagram
Clock Generator
Ramp Generator
Sawtooth
The value of the pull up resistor versus VREF to decrease the oscillator frequency follows the formula:
8.5 10 R 1 ( K ) = -------------------------------------------- + 0.95 400 - F SW ( KHz )
3
In the same way to increase the switching frequency the pull down resistor is selected using the formula:
18 10 R 2 ( K ) = -------------------------------------------- - 2.1 F SW ( KHz ) - 400
3
Table 10 shows some resistor values to adjust the oscillator frequency
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Functional description
L5989D
Table 7.
FSW resistor examples
fSW (kHz) 198 215 245 261 295 322 343 361 R2 (k) 360 180 120 91 56 43 33 27 fSW (kHz) 450 499 548 594 711 801 915 1022
R1 (k) 43 47 56 62 82 110 150 220
To improve the line transient performance, the voltage feed forward is implemented by changing the slope of the sawtooth according to the input voltage change (see Figure 6 a). Figure 6. Sawtooth: voltage feed forward
The slope of the sawtooth does not change if the oscillator frequency is increased by an external signal or adjusted by the external resistor (see Figure 7). As a consequence the gain of the PWM stage is a function of the switching frequency and its contribution must be taken in account when performing the calculations of the compensation network (see Chapter 6.4.1 and Chapter 6.4.2). Figure 7. Sawtooth: frequency adjust
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L5989D
Functional description
5.3
External voltage reference
An external 1.8 V regulated voltage is provided. This reference is useful to set the voltage at the multifunction pin (see Chapter 5.1) or to source current to ILIM-ADJ and FSW pins (see and Chapter 5.5.2). The typical current capability is 4 mA.
5.4
Soft-start
When VCC is above the selected UVLO threshold the start-up phase takes place. At startup, a voltage ramp is generated charging the external capacitor CSS with an internal current generator. The device is in inhibit mode as long as SS/INH pin is below the INH threshold. The L5989D implements the soft-start phase by clamping the output of the error amplifier and, being based on a voltage mode control, the duty cycle. In fact the comparison between the output of the error amplifier and the internal saw tooth waveform generates the duty cycle needed to keep the output voltage in regulation. Two different current sources charge the external capacitor depending on the pin voltage in order to reduce the power consumption in INH mode.
I SS1 = 5 A I SS = I SS2 = 2 2A
0 < V SS/INH < 1 1 < V SS/INH < 2.9
The equation for the soft-start time is:
C SS C SS T SS = T 1 + T 2 = ---------- x ( 1 - 0 ) + ---------- x ( 2.9 - 1 ) I SS1 I SS2
Considering ISS2/ISS1 = 22/5 = 4.4, the proper soft-start capacitor is simply calculated as follows:
C ( nF ) = Tss ( mS ) x 3.5
During the soft-start phase (VSS < 2.9 V):

the sink capability is always disabled (independently from the multifunction pin settings) to be compatible with pre-biased output voltage in case the overcurrent limit is detected, a constant current protection is provided in order to deliver extra current for charging the output capacitor (see Chapter 5.5.2 for description of current protection management).
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Functional description
L5989D
During normal operation the CSS is discharged with a constant current of 22 A (typ.) only if:

HICCUP mode is triggered (see Chapter 5.5.2) the input voltage goes below the UVLO threshold (see Chapter 5.5.3) the internal temperature is over 150C (see Chapter 5.5.4)
A new SS cycle will start when the VSS drops below the INH threshold. New high performance ICs often require more than one supply voltage. Most of these applications require well defined start-up sequencing, in order to avoid potential damage and latch-up of the processing core. Sharing the same soft-start capacitor for a set of regulators, the output voltages increase with the same slew rate implementing a "simultaneous start-up" sequencing method.
5.5
5.5.1
Monitoring and protections
Overvoltage
The device provides the overvoltage protection monitoring the output voltage through the FB pin. If the voltage sensed on FB pin reaches a value 20% (typ.) greater than the reference of the error amplifier, the low-side MOSFET is turned on to discharge as fast as possible the output capacitor. It is possible to set two different behaviors in case of OVP:
In case the OVP latched mode is active (see Chapter 5.1), the internal oscillator is suspended and the low side switch will be kept on until the input voltage goes below the selected UVLO threshold or the SS/INH pin is forced below the INH threshold. In case of NOT latched OVP mode is active, the low side MOS is forced ON until the feedback voltage is higher than the OVP threshold (20% greater than the reference of the error amplifier). OVP not latched
Figure 8.
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L5989D
Functional description Figure 9. OVP latched
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Functional description
L5989D
5.5.2
Current limiting
The current limiting feature acts in different ways depending on the operative conditions.
In case an overcurrent detection happens after the soft-start phase, the internal logic will trigger the "HICCUP" mode. Both switches are turned off and the soft-start capacitor is discharged with a constant current of 22 A (typ.). When the SS/INH voltage drops below the INH threshold a new SS cycle will start. During the soft-start phase the overcurrent information is used to provide a constant current protection. In this way additional current is available to charge the output capacitor during power up.
The most common way is to sense the current flowing through the power MOSFETs. However, due to the noise created by the switching activity of the power MOSFETs, the current sense is disabled during the initial phase of the conduction time. This avoids an erroneous detection of a fault condition. This interval is generally known as "masking time" or "blanking time". For this reason, the current cannot be sensed through the high-side MOSFET in the case of extremely low duty cycles, nor through the low-side MOSFET in the case of very high duty cycles. The L5989D assures the effective protection sensing the current flowing in both embedded switches. The protection achieved by sensing the current in the high-side MOSFET is called "peak overcurrent protection", while the protection achieved by sensing the current in the low-side MOSFET is called "valley overcurrent protection". When the current limit is reached during normal operation, the so called HICCUP mode is triggered, and the soft-start cap is discharged and recharged. However, during the start-up phase, additional current is required to charge the output capacitor. This could continuously trigger the HICCUP intervention preventing the system from reaching a steady working condition. For this reason the HICCUP feature is disabled during the start-up phase and a constant current mode is active to charge the output capacitor. In this case, when the peak current limit is triggered after a conduction time equal to the "masking time", the high-side MOSFET is turned off and the low side MOSFET is kept on until the flowing current goes below the "valley" current limit. If necessary, some switching pulses are skipped, as illustrated in Figure 10. Thus, the combination of the "peak" and "valley" current limits assure the effectiveness of the overcurrent protection even in extreme duty cycle conditions. The current threshold of the low side is designed higher than the high side one to guarantee the proper protection. The constant current mode during the soft-start phase limits the maximum current up to:
V IN - V OUT I MAX = I VALLEY_TH + ----------------------------- T MASK L
The overcurrent limit protection is adjustable (higher or lower than the nominal value) through an external resistor. To guarantee effective protection, both thresholds (valley and peak) are in tracking. The typical active thresholds in case of ILIM-ADJ pin left floating are IPEAK_TH = 4.0 A, IVALLEY_TH = 4.58 A. The dimensioning of the pull up resistor versus VREF to decrease the peak (and valley) thresholds follows the formula:
270.6 R 3 ( k ) = -------------------------------------- , Ipk ( A ) - 4.026 287 Ivy ( A ) = ------------------- + 4.58 R 3 ( k )
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Functional description
In the same way the pull down resistor is selected using the following formula to increase the maximum current thresholds:
120 R 9 ( k ) = -------------------------------------- , 4.026 - Ipk ( A ) 127 Ivy ( A ) = 4.58 - ------------------- R 9 ( k )
Figure 10. Constant current protection at extreme duty cycles
ZOOM
skipped switching pulses
Constant current protection during soft start time soft start time
HICCUP protection Is triggered at the end of the SS time Valley current limit
Table 8 shows some resistor values to adjust the current limits Table 8.
R9(k) 43 47 56 68 91 120 200 560
ILIM-ADJ resistor examples
ILIM PEAK(A) 1.24 1.47 1.88 2.26 2.71 3.03 3.43 3.81 ILIM VALLEY(A) 1.62 1.87 2.31 2.71 3.18 3.52 3.94 4.35 R3(k) 1500 750 470 330 270 220 180 160 ILIM PEAK(A) 4.2 4.38 4.6 4.8 5.0 5.20 5.50 5.70 ILIM VALLEY(A) 4.75 4.95 5.18 5.42 5.62 5.82 6.12 6.30
5.5.3
UVLO
The under-voltage-lock-out (UVLO) is adjustable by the multifunction pin (see Chapter 5.1). It is possible to set two different thresholds:

2.9 V for 3.3 V BUS 8 V for 12 V BUS
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L5989D
5.5.4
Thermal shutdown
When the junction temperature reaches 150 C the device enters in thermal shutdown. Both MOSFETs are turned off and the soft-start capacitor is discharged with a current of 22 A. The device doesn't restart until the junction temperature goes down to 120 C.
5.6
Power Good
An internal comparator monitors the FB to drive the PGOOD open collector output. The voltage reference of the comparator is 85% typ. of the nominal FB voltage (0.6V) and an hysteresis of 5% typ. is provided to increase the noise immunity of the circuitry.
R8 V RISING = 0.85 V FB 1 + ------ R 6 R8 V FALLING = 0.80 V FB 1 + ------ R 6
The PGOOD output is driven in low impedance state as long as the output voltage is lower than VRISING threshold, otherwise released in high impedance. In case the output voltage drops below the VFALLING threshold the PGOOD output goes in low impedance. In case an external type III compensation network is used (see Chapter 6.4.1), the leading network across the resistor R8 could introduce a phase shift of the sensed FB voltage respect to the output voltage during load transitions.
5.7
Minimum on time
The L5989D is based on a voltage mode control loop. The advantage of this technique is the very short conduction time of the power elements thanks to the proper functioning of the control loop without a current sense (that is challenging with low conduction times), which instead is required in current mode regulators. The optimized architecture, the design solutions and the high performance fabrication technique allow power elements to achieve extremely short conduction times. This allows very high switching frequency operation even in very low duty cycle applications. Figure 11 shows how the L5989D can easily manage a minimum conduction time of 200 ns. Moreover, thanks to the embedded P-MOS used for the high-side, no bootstrap capacitor is required. This means that the device is able to manage a duty cycle of 100%.
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Functional description Figure 11. Minimum TON
5.8
Error amplifier
The error amplifier (E/A) provides the error signal to be compared with the sawtooth to perform the Pulse Width Modulation. Its non-inverting input is internally connected to a 0.6 V voltage reference, while its inverting input (FB) and output (COMP) are externally available for feedback and frequency compensation. In this device the error amplifier is a voltage mode operational amplifier so with high DC gain and low output impedance. The uncompensated error amplifier characteristics are the following: Table 9. Uncompensated error amplifier
Low frequency gain GBWP Slew rate Output voltage swing Maximum source/sink current 100 dB 4.5 MHz 7 V/s 0 to 3.3 V 25 mA / 40 mA
In continuos conduction mode (CCM), the transfer function of the power section has two poles due to the LC filter and one zero due to the ESR of the output capacitor. Different kinds of compensation networks can be used depending on the ESR value of the output capacitor. In case the zero introduced by the output capacitor helps to compensate the double pole of the LC filter a type II compensation network can be used. Otherwise, a type III compensation network has to be used (see Chapter 6.4 for details about the compensation network selection). Anyway the methodology to compensate the loop is to introduce zeros to obtain a safe phase margin.
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Application information
L5989D
6
6.1
Application information
Input capacitor selection
The capacitor connected to the input has to be capable to support the maximum input operating voltage and the maximum RMS input current required by the device. The input capacitor is subject to a pulsed current, the RMS value of which is dissipated over its ESR, affecting the overall system efficiency. So the input capacitor must have a RMS current rating higher than the maximum RMS input current and an ESR value compliant with the expected efficiency. The maximum RMS input current flowing through the capacitor can be calculated as:
I RMS = I O D - 2 D - + ------------------- D 2
2
2
Where Io is the maximum DC output current, D is the duty cycles, is the efficiency. This function has a maximum at D = 0.5 and, considering = 1, it is equal to Io/2. In a specific application the range of possible duty cycles has to be considered in order to find out the maximum RMS input current. The maximum and minimum duty cycles can be calculated as:
V OUT + V LOW_SIDE D MAX = ------------------------------------------------------------------------------------------------V INMIN + V LOW_SIDE - V HIGH_SIDE
and
V OUT + V LOW_SIDE D MIN = --------------------------------------------------------------------------------------------------V INMAX + V LOW_SIDE - V HIGH_SIDE
Where VHIGH_SIDE and VLOW_SIDE are the voltage drops across the embedded switches. The peak to peak voltage across the input filter can be calculated as:
IO D D V PP = ----------------------- 1 - --- D + --- ( 1 - D ) + ESR I O C IN f SW
Given a physical dimension, ceramic capacitors can met well the requirements of the input filter substaining an higher input current than electrolytic / tantalum types. In this case the equation of CIN as a function of the target VPP can be written as follows:
IO D C IN = ------------------------ 1 - D D + --- ( 1 - D ) --V PP f SW
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Application information Considering =1 this function has its maximum in D = 0.5:
IO C IN_MIN = --------------------------------------------2 V PP_MAX f SW
Typically CIN is dimensioned to keep the maximum peak-peak voltage across the input filter in the order of 1% VIN_MAX Table 10. Input capacitors
Series GRM31 MURATA GRM55 TDK C3225 10 10 25 25 Cap value (F) 10 Rated voltage (V) 25
Manufacture
6.2
Inductor selection
The inductance value fixes the current ripple flowing through the output capacitor. So the minimum inductance value in order to have the expected current ripple has to be selected. The rule to fix the current ripple value is to have a ripple at 20%-40% of the output current. The inductance value can be calculated by the following equation:
V IN - V OUT V OUT I L = ----------------------------- T ON = -------------- T OFF L L
Where TON and TOFF are the on and off time of the internal power switch. The maximum current ripple, at fixed Vout, is obtained at maximum TOFF that is at minimum duty cycle (see previous section to calculate minimum duty). So fixing IL = 20% to 40% of the maximum output current, the minimum inductance value can be calculated:
V OUT + V F 1 - D MIN L MIN = --------------------------- ---------------------I MAX F SW
where FSW is the switching frequency 1/(TON + TOFF). For example for VOUT = 3.3 V, VIN = 12 V, IO = 4 A and FSW = 400 kHz the minimum inductance value to have IL = 30% of IO is about 4.7 H. The peak current through the inductor is given by:
I L I L, PK = I O + ------2
So if the inductor value decreases, the peak current (that has to be lower than the current limit of the device) increases. The higher is the inductor value, the higher is the average output current that can be delivered, without reaching the current limit.
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Application information In the table below some inductor part numbers are listed. Table 11. Inductors
Series XPL7030 Coilcraft MSS1048 MSS1260 Panasonic ETQP5M4R7YFM WE-HC/HCA Wurth WE-TPC type XLH WE-PD type L DR74 Coiltronics DR125 BI SUMIDA HM78-60 HM78-60 10 4.7 to 10 4.7 to 10 5.3 Inductor value (H) 2.2 to 4.7 2.2 to 6.8 10 4.7 3.3 to 4.7 3.6 to 6.2 10 3.3 to 4.7
L5989D
Manufacturer
Saturation current (A) 6.8 to 10.5 4.14 to 6.62 5.5 8 7 to 11 4.5 to 6.4 5.6 4.3 to 5.4
5.4 to 6.8 5.4 to 6.8
6.3
Output capacitor selection
The current in the capacitor has a triangular waveform (with zero average value) which generates a voltage ripple across it. This ripple is due to the capacitive component and the resistive component (ESR). So the output capacitor has to be selected in order to have a voltage ripple compliant with the application requirements. The amount of the voltage ripple can be calculated starting from the current ripple obtained by the inductor selection.
I MAX V OUT = ESR I MAX + -----------------------------------8 C OUT f SW
Usually the resistive component of the ripple is much higher than the capacitive one, if the output capacitor adopted is not a multi layer ceramic capacitor (MLCC) with very low ESR value. The output capacitor is important also for loop stability: it fixes the double LC filter pole and the zero due to its ESR. In Chapter 6.4, it will be illustrated how to consider its effect in the system stability. For example with VOUT = 3.3 V, VIN = 12 V, IL = 0.6 A (resulting by the inductor value), in order to have a VOUT = 0.01*VOUT, if the multi layer capacitor are adopted, 10 F are needed and the ESR effect on the output voltage ripple can be neglected. In case of not negligible ESR (electrolytic or tantalum capacitors), the capacitor is chosen taking into account its ESR value. So 100 F with ESR = 40 m is compliant with the requested output voltage ripple. The output capacitor is also important to sustain the output voltage when a load transient with high slew rate is required by the load. When the load transient slew rate exceeds the
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L5989D
Application information system bandwidth the output capacitor provides the current to the load. So if the high slew rate load transient is required by the application the output capacitor and system bandwidth have to be chosen in order to sustain load transient and to have a fast response to the transient. In the table below some capacitor series are listed. Table 12. Output capacitors
Series GRM32 MURATA GRM31 ECJ PANASONIC EEFCD SANYO TDK TPA/B/C C3225 10 to 68 100 to 470 22 to 100 6.3 4 to 16 6.3 15 to 55 40 to 80 <5 10 to 47 10 to 22 6.3 to 25 6.3 <5 <5 Cap value (F) 22 to 100 Rated voltage (V) 6.3 to 25 ESR (m) <5
Manufacturer
6.4
Compensation network
The compensation network has to assure stability and good dynamic performance. The loop of the L5989D is based on the voltage mode control. The error amplifier is a voltage operational amplifier with high bandwidth. So selecting the compensation network the E/A will be considered as ideal, that is, its bandwidth is much larger than the system one. The transfer functions of PWM modulator and the output LC filter are studied. The transfer function PWM modulator, from the error amplifier output (COMP pin) to the OUT pin, results:
V IN G PW0 ( f SW0 ) = -------- H ( f SW0 ) Vs
where VS is the sawtooth amplitude and H represent its reliance on the switching frequency. As seen in Chapter 5.2, the voltage feed forward generates a sawtooth amplitude directly proportional to the input voltage, that is:
V S ( f SW0 ) = K V IN H ( f SW0 )
The internal saw tooth is designed in order to have the maximum amplitude at the natural switching frequency of the device. At fSW0 = 400 kHz the PWM modulator can be written as:
V IN 1 G PW0 ( 400 kHz ) = --- = ---------------------------------- = 9 V S ( 400 kHz ) K
The adjustment of the switching frequency through the FSW pin modify the gain of the internal saw tooth (see Chapter 5.2).
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Application information The PWM modulator gain is a function of the switching frequency:
f SW ( kHz ) f SW ( kHz ) G PW0 ( f SW ) = G PW0 ( 400 kHz ) ------------------------- = 18 ------------------------400 400
L5989D
The transfer function on the LC filter is given by:
s 1 + ------------------------2 f zESR G LC ( s ) = -----------------------------------------------------------------------s s ------------------ 2 1 + ---------------------------- + 2 f LC 2 Q f
LC
where:
1 f LC = ----------------------------------------------------------------------- , ESR2 L C OUT 1 + -------------R OUT
1 f zESR = ------------------------------------------2 ESR C OUT
R OUT L C OUT ( R OUT + ESR ) Q = ----------------------------------------------------------------------------------------- , L + C OUT R OUT E SR
V OUT R OUT = -------------I OUT
Two different kind of networks can compensate the loop depending on the output capacitor. Type II network is used to compensate the loop with high ESR output capacitors, type III with low ESR output capacitors (MLCC). In the two following paragraph the guidelines to select the Type II and Type III compensation network are illustrated.
6.4.1
Type III compensation network
The methodology to stabilize the loop consists of placing two zeros to compensate the effect of the LC double pole, so increasing phase margin; then to place one pole in the origin to minimize the dc error on regulated output voltage; finally to place other poles far away the zero dB frequency. In Figure 12 the type III compensation network is shown. This network introduces two zeros (fZ1, fZ2) and three poles (fP0, fP1, fP2). They expression are:
1 f Z1 = ----------------------------------------------- , 2 C 7 ( R 8 + R 7 )
1 f Z2 = ----------------------------2 R 5 C 5
f P0 = 0,
1 f P1 = ----------------------------- , 2 R 7 C 7
1 f P2 = ------------------------------------------C5 C6 2 R 5 ------------------C5 + C6
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L5989D
Application information Figure 12. Type III compensation network
In Figure 13 the bode diagram of the PWM and LC filter transfer function (GPW0 * GLC(f)) and the open loop gain (GLOOP(f) = GPW0 * GLC(f) * GTYPEIII(f)) are drawn. Figure 13. Open loop gain: module bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow:
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Application information 1. 2. Choose a value for R1, usually between 1 k and 5 k.
L5989D
Choose a gain (R5/R8) in order to have the required bandwidth (BW), that means:
BW R 5 = --------- K R 8 f LC
where K is the feed forward constant and 1/K is equals to 9. 3. Calculate C5 by placing the zero at 50% of the output filter double pole frequency (fLC):
1 C 5 = ------------------------- R 5 f LC
4.
Calculate C6 by placing the second pole at four times the system bandwidth (BW):
C5 C 6 = ------------------------------------------------------------2 R 5 C 5 4 BW - 1
5.
Set also the fist pole at four times the system bandwidth and also the second zero at the output filter double pole:
R8 R 7 = -------------------------- , 4 BW ----------------- - 1 f LC 1 C 7 = ---------------------------------------2 R 7 4 BW
The suggested maximum system bandwidth is equals to the switching frequency divided by 3.5 (FSW/3.5), anyway lower than 120kHz if the FSW is set higher than 500 kHz. For example with VOUT = 1.2 V, VIN = 12 V, IO = 4 A, L = 4.7 H, COUT = 47 F, the type III compensation network is:
R 8 = 4.7k, R 6 = 4.7k, R 7 = 180, R 5 = 3.3K, C 7 = 3.3nF, C 5 = 10nF, C 6 = 150pF
In Figure 14 is shown the module and phase of the open loop gain. The bandwidth is about 68 kHz and the phase margin is 50.
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Application information Figure 14. Open loop gain bode diagram with ceramic output capacitor
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Application information
L5989D
6.4.2
Type II compensation network
In Figure 15 the type II network is shown. Figure 15. Type II compensation network
The singularities of the network are:
1 f Z1 = ----------------------------- , 2 R 5 C 5 f P0 = 0, 1 f P1 = ------------------------------------------C5 C6 2 R 5 ------------------C5 + C6
In Figure 16 the bode diagram of the PWM and LC filter transfer function (GPW0 * GLC(f)) and the open loop gain (GLOOP(f) = GPW0 * GLC(f) * GTYPEII(f)) are drawn. Figure 16. Open loop gain: module bode diagram
The guidelines for positioning the poles and the zeroes and for calculating the component values can be summarized as follow:
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L5989D
Application information 1. 2. Choose a value for R8, usually between 1 k and 5 k, in order to have values of C5 and C6 not comparable with parasitic capacitance of the board. Choose a gain (R5/R8) in order to have the required bandwidth (BW), that means:
f ESR 2 BW V S R 5 = ----------- ----------- -------- R 8 f LC f ESR V IN
Where fESR is the ESR zero:
1 f ESR = ------------------------------------------2 ESR C OUT
and Vs is the saw-tooth amplitude. The voltage feed forward keeps the ratio Vs/Vin constant. 3. Calculate C5 by placing the zero one decade below the output filter double pole:
10 C 5 = -----------------------------2 R 5 f LC
4.
Then calculate C7 in order to place the second pole at four times the system bandwidth (BW):
C5 C 7 = ------------------------------------------------------------2 R 5 C 5 4 BW - 1
For example with VOUT = 1.2V, VIN = 12 V, IO = 4 A, L = 4.7 H, COUT = 330 F, ESR = 35 m, the type II compensation network is:
R 8 = 4.7k, R 6 = 4.7K, R 5 = 22k, C 5 = 2.2nF, C 6 = 33pF
In Figure 17 is shown the module and phase of the open loop gain. The bandwidth is about 42 kHz and the phase margin is 56.
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Application information Figure 17. Open loop gain bode diagram with high ESR output capacitor
L5989D
The response of the system to a load transition in terms of output voltage regulation is affected not only by the designed compensation network but it also rely on the selection of the power components (the inductor value, for example, limits the slew rate of the current). Some measurements of the output regulation during load transient for the examples are provided at the end of this document.
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L5989D
Application information
6.5
R.M.S. current of the embedded power MOSFETs
The L5989D integrates both the power elements (high side and low side) and so the power dissipation is often the bottleneck for the output current capability (refer to Chapter 6.6 for the estimation of the operating temperature). Nevertheless, as mentioned in Description on page 6 the device can manage a continuos output current of 4 A in most of the application conditions. However the rated continuos current is 5 A and the rated RMS current of the power elements is 4.5 A, where:
I RMS HS = I LOAD D
I RMS LS = I LOAD 1 - D
and the duty cycle D:
V OUT + ( R DS ON LS + DCR ) I LOAD D = --------------------------------------------------------------------------------------------------V IN + ( R DS ON LS - R DS ON HS ) I LOAD
Fixing the limit of 4.5 A for IRMS HS and IRMS LS the maximum output current can be derived, as illustrated in Figure 18. Figure 18. Maximum continuos output current vs. duty cycle
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L5989D
6.6
Thermal considerations
The thermal design is important to prevent the thermal shutdown of the device if the junction temperature goes above 150 C. The three different sources of losses within the device are: a) conduction losses due to the not negligible RDSON of the power switch; these are equal to:
P ON = R DSON_HS ( I OUT ) D + R DSON_LS ( I OUT ) ( 1 - D )
2 2
Where D is the duty cycle of the application. Note that the duty cycle is theoretically given by the ratio between VOUT an VIN, but actually it is quite higher to compensate the losses of the regulator. So the conduction losses increases compared with the ideal case. b) switching losses due to power MOSFET turn ON and OFF; these can be calculated as:
( T RISE + T FALL ) P SW = V IN I OUT ------------------------------------------ Fsw = V IN I OUT T SW F SW 2
Where TRISE and TFALL represent the switching times of the power element that cause the switching losses when driving an inductive load (see Figure 19). TSW is the equivalent switching time. Figure 19. Switching losses
c)
Quiescent current losses, calculated as:
P Q = V IN I Q
where IQ is the quiescent current.
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L5989D
Application information The junction temperature TJ can be calculated as:
T J = T A + Rth JA P TOT
Where TA is the ambient temperature and PTOT is the sum of the power losses just seen. RthJA is the equivalent static thermal resistance junction to ambient of the device; it can be calculated as the parallel of many paths of heat conduction from the junction to the ambient. For this device the path through the exposed pad is the one conducting the largest amount of heat. The static RthJA measured on the application is about 40 /W. The thermal impedance of the system, considered as the device in HTSSOP16 package soldered on the application board, takes on an important rule when the maximum output power is limited by the static thermal performance and not by the electrical performance of the device. Therefore the embedded power elements could manage an higher current but the system is already taking away the maximum power generated by the internal losses. In case the output power increases the thermal shutdown will be triggered because the junction temperature triggers the designed thermal shutdown threshold. The RTH is a static parameter of the package: it sets the maximum power loss which can be generated from the system given the operation conditions. If we suppose, as an example, TA = 40 C, 140 C is the maximum operating temperature before triggering the thermal shutdown and RTH = 40 C/W so the maximum power loss achievable with the thermal performance of the system will be:
T J MAX - T AMB T100 P MAX DC = ---------- = ------------------------------------- = --------- = 2.5W R TH R TH 40
The switching, conduction and quiescent losses in case of VIN = 12 V, VOUT = 1.2 V, fSW = 400 kHz are plotted in Figure 20. The calculations are performed considering the typical RDS(on) of the power element for a junction temperature of 125 C (RDS_ON HS = 120 m, RDS_ON LS = 83 m; see Maximum ratings on page 8 for details). Conditions: VIN = 12 V, VOUT = 1.2 V, fSW = 400 kHz Figure 20. Estimation of the internal power losses
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Application information
L5989D
The red trace represents the maximum power which can be taken away as calculated above, whilst the purple trace is the total internal losses. As a consequence, given these operating conditions, the system can manage a continuos output current up to 4.2 A. The device could deliver a continuos output current up to 5 A to the load (see Chapter 6.5), however the maximum power loss of 2.5 W is reached with an output current of 4.2 A, so the maximum output power is derated. The calculation of the internal power losses must be done for each specific operating condition given by the final application. For example, the result showed in Figure 20. is not valid in case the VIN is equal to 5 V instead of 12 V: the lower contribution of the switching losses, which are proportional to the input voltage, increases the maximum output current from 4.2 A to 4.5 A (see Figure 21). Conditions: VIN = 5 V, VOUT = 1.2 V, fSW = 400 kHz Figure 21. Estimation of the internal power losses
In applications where the current to the output is pulsed, the thermal impedance should be considered instead of the thermal resistance. Also, in these conditions, the current limitations described in Chapter 6.5 are no more valid since they are related to continuos output current delivery. The thermal impedance of the system could be much lower than the thermal resistance, which is a static parameter. As a consequence the maximum power losses can be higher than 2.5 W if a pulsed output power is requested from the load:
T J MAX - T AMB T P MAX ( t ) = ---------------- = ------------------------------------Z TH ( t ) Z TH ( t )
So, depending on the pulse duration and its frequency, the maximum output current (even more than 5 A) can be delivered to the load.
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Application information The characterization of the thermal impedance is strictly dependent on the layout of the board. In Figure 22. the measurement of the thermal impedance of the evaluation board of the L5989D is provided. Figure 22. Measurement of the thermal impedance of the evaluation board
As it can be see, for example, for load pulses with duration of 1 second, the actual thermal impedance is lower than 20 C/W. This means that, for short pulses, a current higher that 5A (provided the current limitation is set correctly) can be managed.
6.7
Layout considerations
The PC board layout of switching DC/DC regulator is very important to minimize the noise injected in high impedance nodes and interferences generated by the high switching current loops. The L5989D is a monolithic device so most of the critical path are designed internally minimizing the potential issues introduced by the board layout. In the operation of a step down converter two high current loops become evident and critical. The conduction of the high side switch highlight a current loop composed by the input capacitor, the inductor and the output capacitor whilst during the conduction of the low side switch the current flows from the power ground to the inductor and again the output capacitor. The first consideration is to keep the trace of the switching node as short as possible to reduce radiated emission. The bandwidth of the external power supply is limited if compared to the switching frequency of the device so the power supply delivers a certain RMS current in the switching period. As a consequence the input filter substains the input voltage during the conduction time of the
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Application information
L5989D
HS switch delivering an impulsive extra current equal to ILOAD + IRIPPLE - IIN RMS and it is recharged during the conduction time of the low side by the external power supply. The golden rule is to reduce as much as possible the stray inductance of the path related to the capacitor and VINto reduce injected noise: the suggested layout (see Figure 23 and Figure 24) solves this matter placing the input filter just above the package of the device to minimize noise. This placement offers the best filtering for the device and minimize the noise injected by the pulsing current path. The additional stray inductance introduced in the path from the switching node and the external inductor is not critical for the operation of the device. The pin 4 of the L5989D supplies most of the analog circuitry and MOSFET drivers so an RMS current of few mA flows in its trace. A decoupling path between the power and signal input reduces the issues induced by the switching noise: an RC network is helpful to filter the signal supply from the noise generated by the switching activity and it becomes effective when its time constant is bigger than two or three switching cycles. The pin 4 supplies the drivers of the embedded MOSFET so the R value has to be kept limited to avoid voltage spikes during the operation of the embedded driver (the maximum value is in the order of few ohms). The inductor current flows from power GND to the output capacitor during the conduction time of the LS switch: the power ground plane and the signal ground are kept partitioned in the PCB layout to minimize the injected noise on the signal ground. They are connected together below the ground of the output capacitor which is the less noisy power component. The connection of the external resistor divider to the feedback pin (FB) is an high impedance node, so the interferences can be minimized placing the routing of feedback node as far as possible from the high current paths. To reduce the pick up noise the resistor divider has to be placed very close to the device. Thanks to the exposed pad of the device, the ground plane helps to reduce the thermal resistance junction to ambient; so a large ground plane enhances the thermal performance of the converter allowing high power conversion. Figure 23. Top board layout
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Application information Figure 24. Bottom board layout
6.8
Application circuit
In Figure 25 is shown the demonstration board application circuit working. The operating switching frequency is 400 kHz. The designed system bandwidth is 68 kHz with a the phase margin of 50. The peak current limitation is set 5.2 A, the valley current limitation 5.8 A in order to deliver up to 4 A DC to the load. Figure 25. Demonstration board application circuit (fSW = 400 kHz)
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Application information Table 13.
Reference C1 C10 C2A C8 C3 C5 C6 C7 L1 R1 R2 R3 R5 R6 R8 R11 R12 U1 744 311 470
L5989D Component list
Part number GRM32ER61E226KE15 GRM188R71E105KA12 GRM32ER61C476KE15 Description Chip capacitor 22 F 25V Chip capacitor 1F 25V Chip capacitor 47 F 16V Chip capacitor 1 F Chip capacitor 330 nF Chip capacitor 22 nF Chip capacitor 1 nF Chip capacitor 10 nF Inductor 4.7 H Chip resistor 12 k 1% Chip resistor 3.3 k 1% Chip resistor 220 k 1% Chip resistor 1.2 k 1% Chip resistor 4.7 k 1% Chip resistor 4.7 k 1% Chip resistor 4.7 k 1% Chip resistor 5.6 R 1% I.C. L5989D STMicroelectronics Wurth elektronik Manufacturer Murata Murata
In Figure 26. is shown an additional application example where the L5989D operates at a switching of 600 kHz. The designed system bandwidth is 73 kHz with a the phase margin of 51. The peak current limitation is set 5.2 A, the valley current limitation 5.8 A in order to deliver up to 4 A DC to the load.
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L5989D
Application information Figure 26. Demonstration board application circuit (fSW = 600 kHz)
Table 14.
Reference C1 C10 C2A C8 C3 C5 C6 C7 L1 R1 R2 R3 R4 R5 R6 R8 R11 R12 U1
Component list
Part number GRM32ER61E226KE15 GRM188R71E105KA12 GRM32ER61C476KE15 Description Chip capacitor 22 F 25 V Chip capacitor 1 F 25 V Chip capacitor 47 F 16 V Chip capacitor 2.2 F Chip capacitor 330 nF Chip capacitor 22 nF Chip capacitor 1 nF Chip capacitor 10 nF 744 311 330 Inductor 3.3 H Chip resistor 12 k 1% Chip resistor 3.3 k 1% Chip resistor 220 k 1% Chip resistor 82 k 1% Chip resistor 560 1% Chip resistor 1.1 k1% Chip resistor 4.99 k 1% Chip resistor 4.7 k 1% Chip resistor 5.6 1% I.C. L5989D STMicroelectronics Wurth elektronik Manufacturer Murata Murata
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Typical characteristics
L5989D
7
Typical characteristics
Figure 28. Junction temperature vs. fSW
Figure 27. Junction temperature vs. fSW
Figure 29. Junction temperature vs. fSW
Figure 30. Junction temperature vs. VOUT
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Typical characteristics Figure 32. Junction temperature vs. VOUT
Figure 31. Junction temperature vs. VOUT
Figure 33. Efficiency vs. output current
98.00
Figure 34. Efficiency vs. output current
VIN = 5v fSW = 250 kHz
95.00
VIN = 3.3v fSW = 400 kHz
93.00
90.00
88.00
85.00
83.00
(%)
(%)
80.00
78.00
75.00
VIN=5 VOUT=1.2 250 kHz VIN=5 VOUT=1.5 250 kHz VIN=5 VOUT=1.8 250 kHz VIN=5 VOUT=2.5 250 kHz VIN=5 VOUT=3.3 250 kHz
73.00
VIN=3.3 VOUT=1.2 250 kHz VIN=3.3 VOUT=1.5 250 kHz VIN=3.3 VOUT=1.8 250 kHz
68.00
VIN=3.3 VOUT=2.5 250 kHz
70.00
63.00 0.2 0.6 1.0 1.4 1.8 2.2
ILOAD (A)
65.00
2.6
3.0
3.4
3.8
0.2
0.6
1.0
1.4
1.8
2.2
ILOAD (A)
2.6
3.0
3.4
3.8
Figure 35. Efficiency vs. output current
95.00
Figure 36. Load regulation
L5988D LOAD REGULATION (VIN 12V - L = 4.7H)
3.36 3.355
VIN = 12v fSW = 250 kHz
90.00
3.35
85.00
3.345 3.34
80.00
(%)
3.335 (% 3.33 )
VIN=12 VOUT=1.2 250 kHz VIN=12 VOUT=1.5 250 kHz VIN=12 VOUT=1.8 250 kHz VIN=12 VOUT=2.5 250 kHz VIN=12 VOUT=3.3 250 kHz
75.00
3.325 3.32 3.315 3.31 3.305 L5988D_3.3v_400k_AFP]
70.00
65.00
VIN=12 VOUT=5.0 250 kHz
60.00 0.2 0.6 1.0 1.4 1.8 2.2
ILOAD (A)
2.6
3.0
3.4
3.8
3.3 0 0.5 1 1.5 2 ILOAD (A) 2.5 3 3.5 4
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Typical characteristics Figure 37. Line regulation
L5988D LINE REGULATION (L = 4.7H)
3.36 3.355 3.35 3.345 3.34 3.335 (% 3.33 ) 3.325 3.32 3.315 3.31 3.305 3.3 3.5 5.5 7.5 9.5 11.5 ILOAD (A) 13.5 15.5 17.5 L5988D_3.3v_400k
L5989D Figure 38. Load transient from 0 to 3 A
100mV/div
fsw=600 kHz Cout=47uF SR = 2.5A/us
Figure 39. Soft-start
fsw=400 kHz
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L5989D
Package mechanical data
8
Package mechanical data
In order to meet environmental requirements, ST offers these devices in different grades of ECOPACK(R) packages, depending on their level of environmental compliance. ECOPACK(R) specifications, grade definitions and product status are available at: www.st.com. ECOPACK(R) is an ST trademark. Table 15. HTSSOP16 mechanical data
(mm) Dim. A A1 A2 b c D D1 E E1 E2 e L L1 k aaa 0.00 0.45 0.80 0.19 0.09 4.90 2.8 6.20 4.30 2.8 5.00 3 6.40 4.40 3 0.65 0.60 1.00 8.00 0.10 0.75 1.00 Min. Typ. Max. 1.20 0.15 1.05 0.30 0.20 5.10 3.2 6.60 4.50 3.2
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Package mechanical data Figure 40. Mechanical drawing
L5989D
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Order codes
9
Order codes
Table 16. Order codes
Package HTSSOP16 L5989DTR tape and reel Packaging Tube
Order codes L5989D
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Revision history
L5989D
10
Revision history
Table 17.
Date 04-Jun-2009
Document revision history
Revision 1 Initial release Changes
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